This invention relates to a structure and fabrication process of a monolithic opto-electronic integrated circuit using PIN photodiode and junction field effect transistor for improving receiver sensitivity and bit rate.
The important objectives for determining the structure of the opto-electronic integrated circuit for receiving optical signals are, 1) to optimize independently the structure and manufacturing process of the two elements, i.e., the photo-detector and the transistor, both of which require different structures and manufacturing processes, and 2) to connect the elements electrically.
The development stages of the structure of the opto-electronic integrated circuit for receiving optical signals as shown in FIG. 1, is summarized in the order in which development progressed:
FIG. 1a shows a common epi-layer structure where both the photo-detector and the transistor use the same epitaxial layer; PA1 FIG. 1b shows a non-planar structure where the photo-detector and the transistor are integrated in disregard of the differences between their heights; PA1 FIG. 1c shows a groove structure where the position of the optical detector is engraved deeply, since the thickness of the optical detector is thicker than that of the transistor, so that the resulting height of the optical detector and the transistor are the same; PA1 FIG. 1d shows a graded structure wherein the edges of the elements are inclined in order to reduce the problems caused by the differences in their heights above the surface after the etching process; PA1 FIG. 1e shows a planar buried structure where an photo detector is buried in order to make a perfect planar structure; and PA1 FIG. 1f shows a planar compatible structure wherein the structures of the planar type electronic elements as well as their processes stand alone as a result of the optical detector's use with the planar structure.
The processes used for forming the structures of prior art opto-electronic integrated circuits will now be described.
A structure sharing an epitaxial layer (a) is formed by growing a single InGaAs layer on a semi-insulated InP substrate before integrating a PIN optical detector and a junction field effect transistor therein. This is an initial stage of the structure including the first integrated circuit for receiving optical signals. The fabrication of this structure is easy because it only requires one epitaxial growth. However, the performance of the elements in this structure easily deteriorate because it is impossible to independently optimize the structure of the elements due to both the differences in the doping concentrations and the thickness between the PIN photo-detector and the transistor channel layer.
A non-planar structure (b) can be formed by a single epitaxial growth of separate PIN photo detector and FET layers. This structure of the elements can be easily optimized independently of each other because the transistor's channel layer and the optical detector's absorption layer are different. However, if the PIN optical detector is thick, it may cause difficulties in photo-lithography. It is important to note that the PIN detector's absorption layer and the n layer can be etched selectively. This structure presents a similar case to that of (a), in that the parasitic capacitance is also a severe problem.
In the groove type structure (c), since the photo-detector is about 2 to 3 .mu.m thicker than the transistor, the semi-insulated substrate is groove-etched to a depth of 2 to 3 .mu.m before the optical detector is positioned in the groove. This type of the structure has a photo-lithographic advantage compared with the non-planar type structure (b). However, problems still remain in the electrical interconnection between the photo-detector and the transistor. Also, the interconnection capacitance is relatively large.
A graded type structure (d) is a structure for reducing the problems caused by the differences in surfaces' heights. This structure may reduce the problems in photo-lithography and interconnection, as well as the parasitic capacitance. While the elements of this structure perform well, it does have the disadvantage that it requires the graded structure to be manufactured using ion beam etching, which is very difficult.
A planar buried type structure (e) has completely resolved the problems in the difference between the heights of the surfaces so that it accomplishes the photo-lithography process and also reduces the interconnection parasitic capacitance. This structure can be formed by filling an etched groove using either liquid phase epitaxial growth, two ion beam etches, or a selective organo-metallic vapor phase epitaxial growth. In the method that uses the liquid epitaxial growth, the region of the photo-detector was limited. In the method that uses ion beam etching, careful control of the process is required. In the method that uses the selective epitaxial growth, it has the disadvantage that the poly-crystal sometimes grows on the material used as a mask so that the edge portions of the growing region may become over-grown.
In the planar compatible structure (f), a planar photo-detector that uses a substrate as an absorption layer is integrated together with a transistor, such as MESFET. This structure can accomplish the two goals of 1) having a simple manufacturing process and 2) achieving a planar structure. However, the development of the planar photo-detector has not been completed until now. This structure is difficult to manufacture in a InP family which uses an InGaAs layer as an absorption layer.
Other than the structures described above, a vertical structure has been invented in which an n type substrate PIN photo-detector was formed, and a semi-insulated layer was then epitaxially grown thereon before the field effect transistor was formed using an ion implant process. Also disclosed was a method for integrating an InGaAs photo-detector and a GaAs MESFET on a GaAs substrate using a lattice mismatched epitaxy and a method for integrating a GaAs MESFET on an InP substrate.